1. Field of the Invention
The present invention relates to a method for the processing of digital control data associated with an HD-MAC type of video signal as well as to a device for the implementation of this method.
2. Description of the Prior Art
The general problem encountered in the transmission of video signals in high-definition television lies in the fact that the transmission channels are too narrow. Thus, in the case of an HD-MAC type video signal, a bandwidth reduction by a factor of about 4 needs to be obtained. To make this transmission, the participants in the Eureka project have developed and perfected a bandwidth reduction system that performs well, for it achieves an efficient compromise between the restitution of the frame with very good resolution of the frame (spatial definition) and temporal restitution of the frame. The principle chosen consists in adapting the compression mode to the temporal resolution of the frame that has to be transmitted. Depending on the standard chosen, three possible compression modes, called the 80 ms, 20 ms and 40 ms compression modes, are used. Each of these modes preserves the spatial definition or the temporal resolution of the frame, or achieves a compromise between these two qualities. In this case, therefore, an adaptive processing of the video signal is used. To carry out this processing, digital control data has to be transmitted in addition to the video signal. This digital control data contains synchronization information and information on the type of processing to be performed, such as motion vector data or data on the transmission mode. This data is generally known as digital assistance data and is referenced DATV (digitally-assisted television) information. Consequently, the receivers should be capable of decoding this digital control data in order to be capable of processing the HD-MAC type of video signal.
The DATV data associated with an HD-MAC type video signal is therefore decoded in a decoding system such as the one shown in FIG. 1. As described notably in the articles of the IEEE Conference Publication 293 in 1988, the pieces of digital assistance data more particularly include data indicating the transmission mode used or branch decision data, referenced "BD" and motion vector data, referenced MV. All this data is encoded on 11 bits, and concerns a frame block. As shown in FIG. 1, the decoding device has two memories referenced RAM1, RAM2 (RAM=random-access memory), each memory being capable of storing the DATV data corresponding to a processing period, namely an even frame and an odd frame. For the example considered above, each memory has a capacity of at least 6480 eleven-bit words. As shown in FIG. 1, these two memories are connected to the decoder 1. The decoder 1 has a circuit for the control of the memories RAM1 and RAM2. This control circuit receives the DATV data at its input and manages the functioning of the memories RAM1 and RAM2 in reading and writing modes as shall be described hereinafter. The decoder 1 also has a time base 3 which is connected to the control circuit 2 and receives a control signal. The time base emits different synchronization signals respectively referenced SYNCHRO 0, SYNCHRO 1, SYNCHRO 2, . . . , SYNCHRO X towards processing circuits external to the decoder. Furthermore, the decoder 1 has a ROM (read-only memory) 4 in which a decoding table 4 is stored. This memory 4 is connected to the output of the control circuit 2. A multiplexer 5 is connected to the output of the memory 4. At its input, this multiplexer 5 receives the branch decision data BD contained in the DATV data. It respectively receives the branch decision data BD of the odd frame referenced BD-OFR and the branch decision data from the even frame referenced BD-EFR. At its output, it gives a piece of decoded branch decision information that is sent to a delay circuit 6 compensating for the delay due to the processing of the other DATV data as shall be explained in detail hereinafter. At the output of the circuit 6, therefore, a non-delayed piece of branch decision information referenced BD0 is obtained. Furthermore, the output of the memory ROM4 is connected to a motion vector MV data address processing circuit. At its output, this circuit gives the motion vector data, referenced MV-EFR, corresponding to the even frame, and the motion vector data, referenced MV-OFR, corresponding to the odd frame. This data is multiplexed in the multiplexer 8 in such a way that the the non-delayed piece of motion vector data MV0 is obtained at its output. In fact, the DATV data encoded in a processing period corresponding to an even frame and an odd frame, namely 80 ms, is transmitted 80 ms before the corresponding video signal. This explains the use of two memories RAM1 and RAM2, alternately used in reading mode and in writing mode. Thus, during the processing of the DATV data stored beforehand in the the memory RAM1, which then works in reading mode, the DATV data of the next processing period is stored in the memory RAM2 which works in writing mode. With this decoding device, therefore, at the output of the decoder, we obtain the decoded branch decision data BD0 on two bits and the decoded motion vector data MV0 on 8 bits. However, this BD0 and MV0 data should be delayed, for the video signal processing circuit, called a passband reduction decoder, uses also the data BD4, BD2, BD1 delayed respectively by 20 ms, 60 ms, 80 ms with respect to BD0 and the data MV2 which is delayed by 60 ms with respect to MV0 to carry out the appropriate processing of the video signal as a function of the compression mode used. As shown in FIG. 1, this delay is created by using delay circuits such as field memories which may give delays of 20 ms or more. These memories are referenced 9a, 9b, 9c, 9d and 10a, 10b, 10c in FIG. 1. Consequently, the branch decision data BD4 is obtained at the output of the memory 9a, the branch decision data BD2 is obtained at the output of the memory 9c and the branch decision data BD1 is obtained at the output of the memory 9d while the motion vector data MV2 is obtained at the output of the circuit 10c.
Furthermore, as shown in FIG. 1, in addition to the additional assistance data BDX and MVX, the decoder 1 should also generate several time-lagged versions of the synchronization signals. These synchronization signals may notably include line-synchronization, line-parity, field-parity and frame-parity information. These synchronization signals with their specific delay should be connected to different circuits in the processing device of the video signal. The delays may vary from some clock cycles (37 ns) to several line periods (32 .mu.s). Consequently, as shown in FIG. 1, the transmission of all these signals in parallel makes it necessary to have a large number of interconnections on the printed circuit. Furthermore, the delay circuits are made by means of additional integrated circuits. This leads to a high cost for the making of the entire decoding device.
The present invention is therefore aimed at overcoming these drawbacks by proposing a new method for the processing of control digital data associated with an HD-MAC type of video signal as well as a new device for the implementing of this device.